Tech. Details On Memory (RAM)

[Arun Bhardwaj]

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| RAM Feature Type | (SDR) SDRAM | DDR(1) SDRAM |
|-------------------------|----------------------|----------------------|
| Clock frequency | 100/133/166 MHz | 100/133/166/200 MHz |
| Transfer data rate | 100/133/166 MHz | 200/266/333/400 MHz |
| I/O width | ×16 / ×32 | ×4 / ×8 / ×16 / ×32 |
| Prefetch bit width | 1bit | 2bits |
| Clock input | Single clock | Differential clock |
| Burst length | 1, 2, 4, 8, full page| 2, 4, 8 |
| Data strobe | Unsupported | Bidirectional Data |
| | | Strobe (single ended)|
| Supply voltage | 3.3V/2.5V | 2.5V |
| Interface | LVTTL | SSTL_2 |
| CAS latency (CL) | 2, 3 clock | 2, 2.5, 3 clock |
| Read latency | CL | CL |
| Write latency | 0 | 1 |
| Additive latency (AL) | Unsupported | Unsupported |
| Off-chip driver (OCD) | Unsupported | Unsupported |
| On die termination (ODT)| Unsupported | Unsupported |
| Component package | TSOP(II)/FBGA | TSOP(II)/FBGA/LQFP |
| pin (module) | 168pin | 184pin |
| | | |
|-------------------------|----------------------|----------------------|

Code:

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| RAM Feature Type | DDR2 SDRAM | DDR3 SDRAM |
|-------------------------|--------------------------|--------------------|
| Clock frequency | 200/266/333/400 MHz | 400 ~ 800 MHz |
| Transfer data rate | 400/533/667/800 MHz | 800 ~ 1600 MHz |
| I/O width | ×4 / ×8 / ×16 | ×4 / ×8 / ×16 |
| Prefetch bit width | 4bits | 8 bit |
| Clock input | Differential clock | Differential clock |
| Burst length | 4, 8 | |
| Data strobe | Bidirectional Data Strobe| |
| | (single ended or | |
| | differential) with RDQS | |
| Supply voltage | 1.8V | 1.5v |
| Interface | SSTL_1.8 | |
| CAS latency (CL) | 3, 4, 5 clock | |
| Read latency | AL+CL | |
| Write latency | (AL+CL)-1 | |
| Additive latency (AL) | 0, 1, 2, 3, 4 clock | |
| Off-chip driver (OCD) | Support/Present | Support |
| On die termination (ODT)| Support/Present | Support |
| Component package | FBGA | FBGA |
| pin (module) | 240 pin | |
| | | |
|-------------------------|--------------------------|--------------------|

Code:

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| RAM Type | XDR DRAM | DDR4 SDRAM | QDR SDRAM |
|-------------------------|--------------------|------------|-----------|
| Clock frequency | 400 MHz ~ | | |
| Transfer Data Rate | 3.2 GHz ~ | | |
| I/O Width | x16 | | |
| Prefetch bit width | | | |
| Clock Input | Differential clock | | |
| Burst length | | | |
| Data Strobe | | | |
| Supply Voltage | 1.8v | | |
| Interface | | | |
| CAS Latency(CL) | | | |
| Read Latency | | | |
| Write Latency | | | |
| Additive Latecny | | | |
| Off-Chip Driver | Support | | |
| On Die Termination | Support | | |
| Component Package | FBGA | | |
| pin (module) | | | |
| | | | |
|-------------------------|--------------------|------------|-----------|

CAS : Column Address Select/Strobe . The lower the (CL) CAS value, the faster the RAM is .
Faster speed, faster RAM .
The more Data bit width, the more total Bandwidth is .

SDR : Single Data Rate SDRAM . 1 data word in 1 clock cycle (in rising edge) . Single port for read, write .

DDR : Double Data Rate SDRAM . 2 data words in 1 clock cycle (in both rising & falling edge) . Single port for read, write .

XDR : eXtreme Data Rate DRAM . Bi-Directional RSL (DRSL) (Differential Rambus Signaling Levels), FlexPhase, ODR .

QDR : Quad Data Rate SDRAM . 4 data words in 1 clock cycle. Separate read, write port .